Process-induced Structural Variability-aware Performance Optimization for Advanced Nanoscale Technologies

Department of Electrical EngineeringAs the CMOS technologies reach the nanometer regime through aggressive scaling, integrated circuits (ICs) encounter scaling impediments such as short channel effects (SCE) caused by reduced ability of gate control on the channel and line-edge roughness (LER) caused by limits of the photolithography technologies, leading to serious device parameter fluctuations and makes the circuit analysis difficult. In order to overcome scaling issues, multi-gate structures are introduced from the planar MOSFET to increase the gate controllability. The goal of this dissertation is to analyze structural variations induced by manufacturing process in advanced nanoscale devices and to optimize its impacts in terms of the circuit performances. If the structural variability occurs, aside from the endeavor to reduce the variability, the impact must be taken into account at the design level. Current compact model does not have device structural variation model and cannot capture the impact on the performance/power of the circuit. In this research, the impacts of structural variation in advanced nanoscale technology on the circuit level parameters are evaluated and utilized to find the optimal device shape and structure through technology computer-aided-design (TCAD) simulations. The detail description of this dissertation is as follows: Structural variation for nanoscale CMOS devices is investigated to extend the analysis approach to multi-gate devices. Simple and accurate modeling that analyzes non-rectilinear gate (NRG) CMOS transistors with a simplified trapezoidal approximation method is proposed. The electrical characteristics of the NRG gate, caused by LER, are approximated by a trapezoidal shape. The approximation is acquired by the length of the longest slice, the length of the smallest slice, and the weighting factor, instead of taking the summation of all the slices into account. The accuracy can even be improved by adopting the width-location-dependent factor (Weff). The positive effect of diffusion rounding at the transistor source side of CMOS is then discussed. The proposed simple layout method provides boosting the driving strength of logic gates and also saving the leakage power with a minimal area overhead. The method provides up to 13% speed up and also saves up to 10% leakage current in an inverter simulation by exploiting the diffusion rounding phenomena in the transistors. The performance impacts of the trapezoidal fin shape of a double-gate FinFET are then discussed. The impacts are analyzed with TCAD simulations and optimal trapezoidal angle range is proposed. Several performance metrics are evaluated to investigate the impact of the trapezoidal fin shape on the circuit operation. The simulations show that the driving capability improves, and the gate capacitance increases as the bottom fin width of the trapezoidal fin increases. The fan-out 4 (FO4) inverter and ring-oscillator (RO) delay results indicate that careful optimization of the trapezoidal angle can increase the speed of the circuit because the ratios of the current and capacitance have different impacts depending on the trapezoidal angle. Last but not least, the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using device simulations are also investigated in this work. The DGAA FET, a kind of nanotube field-effect transistor (NTFET), can solve the problem of loss of gate controllability of the channel and provide improved short-channel behavior. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, this work proposes the n/p DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional GAA inverter structure. In the optimum structure, 27% propagation delay and 15% leakage power improvement can be achieved. Analysis and optimization for device-level variability are critical in integrated circuit designs of advanced technology nodes. Thus, the proposed methods in this dissertation will be helpful for understanding the relationship between device variability and circuit performance. The research for advanced nanoscale technologies through intensive TCAD simulations, such as FinFET and GAA, suggests the optimal device shape and structure. The results provide a possible solution to design high performance and low power circuits with minimal design overhead.ope

Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width

We investigate the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a siliconnanotube field-effect transistor (NTFET) with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.ope

Quantitative Analysis of Peripheral Tissue Perfusion Using Spatiotemporal Molecular Dynamics

Background: Accurate measurement of peripheral tissue perfusion is challenging but necessary to diagnose peripheral vascular insufficiency. Because near infrared (NIR) radiation can penetrate relatively deep into tissue, significant attention has been given to intravital NIR fluorescence imaging. Methodology/Principal Findings: We developed a new optical imaging-based strategy for quantitative measurement of peripheral tissue perfusion by time-series analysis of local pharmacokinetics of the NIR fluorophore, indocyanine green (ICG). Time-series NIR fluorescence images were obtained after injecting ICG intravenously in a murine hindlimb ischemia model. Mathematical modeling and computational simulations were used for translating time-series ICG images into quantitative pixel perfusion rates and a perfusion map. We could successfully predict the prognosis of ischemic hindlimbs based on the perfusion profiles obtained immediately after surgery, which were dependent on the preexisting collaterals. This method also reflected increases in perfusion and improvements in prognosis of ischemic hindlimbs induced by treatment with vascular endothelial growth factor and COMP-angiopoietin-1. Conclusions/Significance: We propose that this novel NIR-imaging-based strategy is a powerful tool for biomedical studies related to the evaluation of therapeutic interventions directed at stimulating angiogenesis

Analysis of Structural Variation and Threshold Voltage Modulation in 10-nm Double Gate-All-Around (DGAA) Transistor

Increasing short channel effects (SCE) interrupt the further technology scaling in the CMOS transistors. Beyond 10 nm technology node, the gate-all-around (GAA) FET is considered as a promising solution for continuing the Moore's law. In this paper, we report the analysis of the double gate-all-around (DGAA) FET in terms of structural variations and the effect of the threshold voltage modulation by independently controlled inner gate. The impact of inner gate thickness and gate oxide thickness variations on the electrical characteristic of the DGAA FET are investigated. In addition, we propose the inner gate utilization to modulate the threshold voltage of the transistor for providing more design options

Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape

In this paper, a simple and accurate modeling technique that analyzes a non-rectilinear gate (NRG) transistor with a simplified trapezoidal approximation method is proposed. To approximate a non-rectangular channel shape into a trapezoidal shape, we extract three geometry-dependent parameters from post-lithographic patterns: the minimum channel length from the slices (Lmin), maximum channel length from the slices (Lmax), and effective channel width (Weff). We slice the NRG transistor gate along its width, sort these slices according to their sizes, and then use trapezoidal approximation. A physics-based technology computer aided design (TCAD) simulation is used to verify our model in a typical 45-nm process. The developed model requires fewer computations and less runtime as compared to the previous approaches. Therefore, a full chip post-lithography analysis (PLA) becomes feasible.open0

Junctionless Sandwiched-gate Logic Design using Novel Device Structure

In this paper, a novel sandwiched-gate logic family that is based on a sandwiched-gate inverter, which consists of an NMOS Gate-All-Around (GAA) together with a donut-type PMOS GAA, is proposed. For the realization of the proposed vertical structure, a junctionless configuration is suggested with the absence of the channel- doping process. The ratio of the thickness of the NMOS and the PMOS determines the switching threshold in the sandwiched-gate inverter. The direct-current (DC) operation and the transient performance of the sandwiched-gate inverter are investigated with 3D technology computer-aided-design (TCAD) simulations. The sandwiched- gate inverter exhibits a correct inverter operation with a high noise margin and a fast transition speed. To extend the proposed architecture to other logic gates, the proposed sandwiched-gate structure is also applied to fundamental logic circuits such as the NAND, NOR, and SRAM cell designs, and each operation is verified. The proposed logic gates achieve up to a 20% area reduction compared with the conventional GAA

A high resolution and high linearity 45 nm CMOS fully digital voltage sensor for low power applications

This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high linearity and high resolution. The proposed CDE uses power supply node to measure the voltage value. However, the delay increases exponentially at low voltage level. In this paper we add a PMOS header in parallel with the conventional CDE to compensate the delay degradation at lower voltage. We develop a 16-levels fully digital voltage sensor with a voltage range of 0.8 ~ 1.1V and 20mV resolution by using of the proposed delay elements. The proposed circuit is designed and simulated in a 45nm CMOS process. The simulation results show the feasibility of the high resolution and high linearity at low voltage by using of the proposed delay elements.open0

Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from 10 degrees to 20 degrees is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shapeclose

Comprehensive Performance Analysis of Interconnect Variation by double and triple patterning lithography processes

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.close0

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

Increasing short channel effects (SCEs) hinder further technology downscaling of CMOS transistors. Beyond the 10-nm technology node, the gate-all-around (GAA) FET is considered a promising solution for continuing Moore's law. In this study, we introduce a novel structure for speeding up the interconnect propagation using 10-nm channel length double gate-all around (DGAA) transistors. We propose a boosting structure that can significantly improve the performance of circuits by controlling the two gates of the DGAA independently. The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role in application-specific integration circuits in future GAA-based designsopen0